Aldec’s Riviera 2002.09 Increases Simulation Performance for ASIC and SoC Designs

Henderson Nevada, October 21st, 2002 - Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, announced today the release of Riviera 2002.09, improving simulation performance and adding new advanced debugging features, such as the Design Profiler and Signal Agent, to increase overall design productivity. Riviera is based on Aldec’s industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers for the new generation of system-on-chip designs.

3x Performance Gains
Aldec has reached a new level of verification performance with the release of 2002.09; new development methods and additional performance optimizations yield simulation speed improvements as much as 3x for VHDL, Verilog, and mixed designs. Analyzing the most common design styles in the industry and optimizing how the simulator can most efficiently verify ASIC and SoC designs have achieved these performance improvements.

“With the release of 2002.09, we have not only focused on increased simulation performance with new development methodologies, but have added several new features that our customers have been requesting,” stated Eric Seabrook, Product Marketing Manager for Aldec, adding, “Riviera is rapidly being accepted as an industry-leader for mixed simulation and the features added in 2002.09 provide even more advanced debugging features.”

Optimize Verification Run-Times
Riviera’s simulation performance increase is in part accomplished by providing a series of performance optimization switches, giving the designer the ability to simulate only those selected signals that he or she is monitoring at the time. The simulator only collects the debug data that is requested by the designer, allowing Riviera to run in a highly optimized mode in excess of 10x and providing the user with debugging information that is relevant to the monitored signals only. This provides a significant advantage for million-gate designs that do not require the simulator to collect information on every signal of the design.

Design Profiler
The Design Profiler provides information on CPU usage during simulation and isolates HDL modules that are creating bottlenecks in simulation run time. The modules that are shown to be inefficient can then be evaluated and made more effective, making the overall verification time much faster. The Design Profiler allows users to pinpoint areas of the design that decrease design efficiency, ensuring that all modules are fully-optimized.

Signal Agent
The Signal Agent allows designers to monitor and drive signals from any hierarchical level. The Signal Agent joins the source signals with the destination signals and operates as if the signals were connected directly in HDL. Instead of having to modify the source code directly, designers can indicate which signals they want saved to a file. Signals can be read within the top-level hierarchy as well as accessed from inside the testbench. This procedure enhances debugging and simplifies testbench development while protecting the integrity of the HDL code.

New Waveform Viewer
The Waveform Viewer has been completely redesigned to include better file handling and optimization, accelerated waveform generation and viewing, additional comparison enhancements, and Print on Change (.lst) file output used by ASIC foundries. These additions increase debugging accuracy, performance, and productivity.

Code Coverage
The Code Coverage feature has been enhanced to include a coverage merge feature. This allows the designer to take different coverage results and consolidate them into a single file. The file containing multiple stimuli information can then be analyzed and debugged for a more efficient testbench. The merge feature is of particular importance to designers who segment the testbench into smaller, more manageable blocks because all stimuli results can be combined for debugging purposes.

Partner Interfaces
Riviera now includes an interactive interface to Summit Design’s Visual Elite 3.0, extended support for SWIFT DesignWare models, Cadence TestBuilder C++ testbench libraries, and overall VHPI/PLI optimization. Enhanced install scripting for Verisity Specman-Elite and Denali PureView are also included to make tool connection simple.

Availability
Riviera 2002.09 is available today based on a cross-platform, floating license that supports UNIX, Windows and Linux. Riviera includes Aldec’s industry-proven mixed VHDL and Verilog simulation engine, which supports IEEE VHDL 1076-87/93 and Vital 2000 in addition to Verilog 1376-95 and 2001. Riviera is a comprehensive verification tool and includes Code Coverage, Design Profiler, Signal Agent, as well as interfaces to all leading EDA tools for no additional cost. Riviera is sold directly by Aldec in the U.S. and authorized international distributors. For a FREE evaluation copy of Riviera, go to www.aldec.com/riviera.

About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.


Riviera is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Contact:        
Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224        
erics@aldec.com